NXP 74HC Series Logic Devices
- NXP 74HC573D, 652, The 74HCT573D has octal D-type transparent latches featuring separate D-type inputs for each latch & 3-state true outputs for bus-oriented applications. A latch enable (LE) input & an output enable (OE) input are common to all latches. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74HCT573 is a high-speed Si-gate CMOS device & is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. NXP 74HC573D, 652 SMD HCMOS Octal D-Type Latch Non-Inverting Tri-Stat SO-20