. .. FBGA components. The SPD is programmed to JEDEC standard latency DDR4-2400 timing of 17-17-17 at 1.2V. Each 260-pin SODIMM uses gold contact fingers. Features Power Supply: VDD=1.2VVDDQ = 1.2VVPP
- 2.5VVDDSPD=2.2V to 3.6 V Functionality & operations comply with the DDR4 SDRAM datasheet 16 internal banks Bank Grouping is applied, & CAS to CAS latency (t CCD_L, t CCD_S) for the banks in the same or different bank group accesses are available Data transfer rates: PC4-2400, PC4-2133, PC4-1866, PC4-1600 Bi-directional Differential Data Strobe 8-bit pre-fetch Burst Length (BL) switch on-the-fly BL8 or BC4 (Burst Chop) Supports ECC error correction & detection On-Die Termination (ODT) Temperature sensor with integrated SPDThis product is in compliance with the Ro HS directive Per DRAM Addressability is supported Internal Vref DQ level generation is available Write CRC is supported at all speed grades CA parity (Command/ Address Parity) mode is supported Ro HS Compliant & Halogen-Free Extra Info Memory
Size: 8192MBModule
Size: 8192MBMemory Type: DDR4 Memory Package: SO-DIMMPin Configuration: 260 pins Main
Colour: Green